1. Field of the Invention
This invention relates to semiconductor device packages. More particularly, this invention relates to reversible leadless semiconductor device packages and methods for manufacturing reversible leadless semiconductor device packages.
2. Description of the Related Art
In lead frame based semiconductor device packages, electrical signals are transmitted between at least one semiconductor device (die) and external circuitry, such as a printed circuit board, by an electrically conductive lead frame. The lead frame includes a plurality of leads, each having an inner lead end and an opposing outer lead end. The inner lead end is electrically connected to an input/output (I/O) pad on the die, and the outer lead end provides a terminal for connecting to the external circuitry. Where the outer lead ends terminate at a face of the package body, the package is known as a “no-lead” or “leadless” package. If the outer lead ends extend beyond the package body perimeter, the package is referred to as “leaded.” Examples of well-known no-lead packages include quad flat no-lead (QFN) packages, which have four sets of leads disposed around the perimeter of the bottom of a square package body, and dual flat no-lead (DFN) packages, which have two sets of leads disposed along opposite sides of the bottom of a package body.
A method for manufacturing a lead frame for a Quad Flat No-lead (“QFN”) package is disclosed in U.S. Pat. No. 6,498,099 to McLellan et al., which is incorporated by reference in its entirety herein. In the McLellan et al. patent, a first side of an electrically conductive substrate is partially etched to define a support pad and inner lead ends. A semiconductor device is bonded to the partially defined support pad and electrically interconnected to the partially defined inner lead ends by wire bonds or the like. The semiconductor device, partially defined support pad, partially defined inner leads and wire bonds are then encapsulated in a polymer molding resin. The opposing second side of the electrically conductive substrate is then etched to electrically isolate the support pad and inner lead ends and to define outer lead ends.
Another method for the manufacture of a QFN package is disclosed in commonly owned U.S. patent application Ser. No. 10/134,882 that was filed on Apr. 29, 2002 and is incorporated by reference in its entirety herein.
There is a desire in the semiconductor packaging industry to minimize the profile height (thickness) of semiconductor packages to facilitate advances in mobile, wireless, and medical applications. Current demands are for packages having profile heights in the sub-millimeter level. A need for increased processing power and speed has also created a demand to increase the number of dies that can be fit into a given area (i.e., to increase die density) and to decrease the length of the electrical path between dies.
One solution to the demands for increased die density and decreased electrical path length is to stack a number of dies inside a single package. The dies are separated by insulating layers/interposers with wire-bond and/or flip-chip die connections used to electrically connect the dies to a common lead frame. This solution, however, has its drawbacks. First, a package with stacked dies introduces complexity in the assembly of the package due at least in part to the increased number of electrical connections within the package and the need for an insulative layer/interposer to be disposed between the dies. If any defects occur during the assembly of the package, the entire package, including all chips within the stack, is unsalvageable. Second, where a wirebonding process is used to electrically connect the stacked dies, the top die in the stack must be sized to provide sufficient peripheral space on the bottom die to allow for wirebonding the bottom die. In other words, the top die must be smaller than the bottom die. Finally, stacking two or more dies in a single package increases the thickness of the encapsulated package and creates issues for power management and thermal drain.
Thus there remains a need for semiconductor device packages having a decreased profile while allowing for an increased die density and a decreased length of the electrical path between dies.